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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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Features
* * * Using external 32.768kHz quartz crystal Supports I2C-Bus's high speed mode (400 kHz) Includes time (Hour/Minute/Second) and calendar (Year/Month/Date/Day) counter functions (BCD code) * * * * Automatic power-fail detect and switch circuitry of battery backup Operating range: 2.0V to 5.5V Software clock calibration Ultra-low battery supply current of 1A
Description
The PT7C4300 serial real-time clock is a low-power clock/calendar with a programmable square-wave output.
Address and data are transferred serially via a 2-wire bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in the 24hour format indicator. Table 1 shows the basic functions of PT7C4300. More
Ordering Information
Part Number PT7C4300W PT7C4300WE Package 8-Pin SOIC Lead free 8-Pin SOIC
details are shown in section: overview of functions.
Table 1. Basic functions of PT7C4300 Item Function Source: Crystal: 32.768kHz 1 Oscillator Oscillator enable/disable Oscillator fail detect 12-hour Time display 24-hour Century bit Time count chain enable/disable 3 4 5 6 7 Programmable square wave output (Hz) Programmable high/low level output Communicat ion Battery backup Clock calibration 2-wire I C bus 3-wire bus Burst mode
2
PT7C4300 512Hz
2
Time
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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Function Block
Recommended Layout for Crystal
PT7C4300 PT7C4307
Local Ground plane Layer 2 Guard Ring (connect to gound)
Crystal Specifications
Parameter Nominal Frequency Series Resistance Load Capacitance Symbol fO ESR CL Min Typ 32.768 12.5 Max 40 Unit kHz k pF
The crystal, traces and crystal input pins should be isolated from RF generating signals.
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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Pin Configuration
Pin Description
Pin no. 1 Pin X1 Type I Description Oscillator Circuit Input. Together with X1, 32.768kHz crystal is connected between them. Or external clock input. Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between them.
2
X2
O
3
VBAT
P
Battery Supply Voltage.
4
GND
P
Ground. Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The SDA pin is open-drain output and requires an external pull-up resistor. Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface. Frequency Test / Output Driver. Open drain. 512Hz output when Frequency Test is selected. Output DC level by register selection. Frequency Test is prior. Supply Voltage.
5
SDA
I/O
6
SCL
I
7
FT/OUT
O
8
VCC
P
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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Function Description
Overview of Functions
1.
Clock function
CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100.
2.
Interface with CPU
Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data). Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is also open drain. The SCL's maximum clock frequency is 400 kHz, which supports the I2C bus's high-speed mode.
3.
Oscillator enable/disable
Oscillator and time count chain can be enabled or disabled at the same time by ST bit.
4.
Calibration function
With the calibration bits properly set, accuracy PT7C4300 can be improved to better than 2 ppm at 25C.
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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Registers
1. Allocation of registers Register definition Addr. (hex) *1 Function Bit 7 ST*2 x CEB*3 x x x Y80 OUT*4 Bit 6 S40 M40 CB*3 x x x Y40 FT*5 Bit 5 S20 M20 H20 x D20 x*8 Y20 S*6 Bit 4 S10 M10 H10 x D10 MO10 Y10 Bit 3 S8 M8 H8 x D8 MO8 Y8 Bit 2 S4 M4 H4 W4 D4 MO4 Y4 Calibration*7 Bit 1 S2 M2 H2 W2 D2 MO2 Y2 Bit 0 S1 M1 H1 W1 D1 MO1 Y1
00 01 02 03 04 05 06 07
Seconds (00-59) Minutes (00-59) Hours (00-23) Days of the week (01-07) Dates (01-31) Months (01-12) Years (00-99) Control*3
Caution points: *1. PT7C4300 uses 3 bits for address. That is if write data to 08H, the data will be written to 00H address register. *2. Stop bit. When this bit is set to 1, oscillator and time count chain are both stopped. *3. CEB: Century Enable Bit. CB: Century Bit. *4. Control FT/OUT pin output DC level when 512Hz square wave is disabled. *5. Frequency Test. 512Hz square wave output is enabled at FT/OUT pin, which is using for frequency test. *6. Sign Bit. "1" indicates positive calibration; "0"indicates negative calibration. *7. Using for modifying count frequency. If 20ppm is wanted to slow down the count frequency, 10 (01010) should be loaded. Calibration will not affect FT/OUT output frequency. *8. Don't care.
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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2.
Control and status register
Addr. (hex) 07
Description Control (default)
D7 OUT 0
D6 FT 0
D5 S 1
D4
D3
D2 Calibration 1
D1
D0
1
1
1
1
a) OUT * OUT: Set pin 7 output DC level.. OUT Data 1 Read / Write 0 Set low level at pin 7. Set high level at pin 7.
Description Default
b) 512Hz output * FT: 512Hz square wave output Enable bit, using for Frequency Test. FT Data 0 Read / Write 1 c) * Calibration bits S: Sign bit. S Read / Write 0 Indicate negative calibration. Enable 512Hz output at pin 7. Disable 512Hz output at pin 7.
Description Default
Data 1 Indicate positive calibration.
Description Default
Calibration: Calibration occurs within a 64minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. For example, a reading of 512.01024Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (XX001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. Clock calibration
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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3.
Time Counter
Time digit display (in BCD code): * Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. * Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00. * Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. Addr. (hex) 00 01 02 Description Seconds (default) Minutes (default) Hours (default) D7 ST 0 x*2 0 CEB*3 0 D6 D5 D4 D3 D2 D1 D0
S40 S20 S10 S8 S4 S2 S1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined M40 M20 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined CB*3 0 H20 H10 H8 H4 H2 H1 Undefined Undefined Undefined Undefined Undefined Undefined
* Note 1: ST bit: Stop oscillation and time count chain. * Note 2: Do not care. * Note 3: Century Enable Bit and Century Bit.
4.
Days of the week Counter
The day counter is a divide-by-7 counter that counts from 00 to 06 and up 06 before starting again from 00. Values that correspond to the day of week are user defined but must be sequential (i.e., if 0 equals Sunday, then 1 equals Monday, and so on). Illogical time and date entries result in undefined operation. The day counter is a divide-by-7 counter that counts from 01 to 07 and up 07 before starting again from 01. Values that correspond to the day of week are user defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. Addr. Description D7 D6 D5 D4 D3 D2 D1 D0 (hex) 03 x Days of the week (default) Undefined x Undefined x Undefined x Undefined x W4 W2 W1 Undefined Undefined Undefined Undefined
5.
Calendar Counter
The data format is BCD format. * Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December). Range from 1 to 30 (for April, June, September and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). Carried to month digits when cycled to 1. * Month digits: Range from 1 to 12 and carried to year digits when cycled to 1. * Year digits: Range from 00 to 99 and 00, 04, 08, ... , 92 and 96 are counted as leap years.
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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Addr. (hex) 04 05 06
Description Dates (01-31) (default) Months (01-12) (default) Years (00-99) (default)
D7
D6
D5
D4
D3
D2
D1
D0
x x D20 D10 D8 D4 D2 D1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined x x x M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Communication
1. a) I2C Bus Interface Overview of I2C-BUS
The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on. Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its slave address matches the slave address in the received data. b) System Configuration
All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices. SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high level when the bus is released (when communication is not being performed).
V cc RP RP
SD A SCL
M aster M CU
Slave R TC
O ther Peripheral D evice
N ote: W hen there is only one m aster, the M CU is ready for driving SCL to "H " and R P of SCL m ay not required.
Fig.1 System configuration PT0222(02/06) 8 Ver: 0
Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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c)
Starting and Stopping I2C Bus Communications
Fig.2 Starting and stopping on I2C bus START condition, repeated START condition, and STOP condition * START condition SDA level changes from high to low while SCL is at high level * STOP condition SDA level changes from low to high while SCL is at high level * Repeated START condition (RESTART condition) In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the START condition, the SDA level changes from high to low while SCL is at high level. d) Data Transfers and Acknowledge Responses during I2C-BUS Communication
* Data transfers Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. The address auto increment function operates during both write and read operations. Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level. The receiver (receiving side) captures data while the SCL line is at high level.
*Note: with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART, or STOP condition.
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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* Data acknowledge response (ACK signal) When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This does not include instances where the master device intentionally does not generate an ACK signal.) Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
SCL from Master
1
2
8
9
SDA from transmitter (sending side)
Release SDA
SDA from receiver (receiving side)
Low active ACK signal
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the transmitter. When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a STOP condition from the Master. e) Slave Address
The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device. All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device responds to this communication only when the specified slave address it has received matches its own slave address. Slave addresses have a fixed length of 7 bits. See table for the details. An R/W bit is added to each 7-bit slave address during 8-bit transfers. Operation Read Write Transfer data bit 7 D1 h D0 h 1 bit 6 1 bit 5 0 Slave address bit 4 1 bit 3 0 bit 2 0 bit 1 0 R / W bit bit 0 1 (= Read) 0 (= Write)
2.
I2C Bus's Basic Transfer Format
S
Start indication
P
Stop indication
A
RTC Acknowledge
Sr
Restart indication
A
Master Acknowledge
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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a)
Write via I2C bus
S 1
Start
Slave address (7 bits) 1 0 1 0 0 0
write
A
Addr. setting
A
bit
bit
bit
bit
bit
bit
bit
bit
0
A C K
7
6
5
4
3
2
1
0
A
P
Slave address + write specification
Address Specifies the write start address.
A C K
Write data
A C K
Stop
b) *
Read via I2C bus Standard read
S 1
Start
Slave address (7 bits) 1 0 1 0 0 0
write
A
Addr. setting
A
0
A C K
Slave address + write specification
Address Specifies the read start address.
A C K
Sr 1
Restart
Slave address (7 bits) 1 0 1 0 0 0
Read
A
bit
bit
bit
bit
bit
bit
bit
bit
1
A C K
7
6
5
4
3
2
1
0
A
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
/A
P
Slave address + read specification
Data read (1) Data is read from the specified start address and address auto increment.
A C K
Data read (2) Address auto increment to set the address for the next data to be read.
N O A C K
Stop
*
Simplified read
S 1
Start
Slave address (7 bits) 1 0 1 0 0 0
Read
A
bit
bit
bit
bit
bit
bit
bit
bit
1
A C K
7
6
5
4
3
2
1
0
A
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
/A
P
Slave address + read specification
Data read (1) Data is read from the address pointed by the internal address register and address auto increment.
A C K
Data read (2) Address register auto increment to set the address for the next data to be read.
N O A C K
Stop
Note: 1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications. 2. 49H, 4AH are used as test mode address. Customer should not use the addresses.
PT0222(02/06) 11
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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3.
Data Retention Mode
With valid VCC applied, the PT7C4300 can be accessed as described above with READ or WRITE Cycles. Should the supply voltage decay, the PT7C4300 will automatically deselect, write protecting itself when VCC falls.
Sym. Parameter Min Max Unit tPD SCL and SDA at VIH before Power Down 0 ns tREC SCL and SDA at VIH after Power Up 10 s Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.0 to 5.5V (except where noted). 2. VCC fall time should not exceed 5mV/s.
PT0222(02/06) 12
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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Maximum Ratings
Storage Temperature.......................................................................................................................-65oCto +150oC Ambient Temperature with Power Applied...........................................................................-40oCto +85oC Supply Voltage to Ground Potential (Vcc to GND) ..........................................................-0.3V to +6.5V DC Input (All Other Inputs except Vcc & GND)................................................................-0.3V to (Vcc+0.3V) DC Output Voltage (SDA, /INTA, /INTB pins)..................................................................-0.3V to +6.5V Power Dissipation............................................................................................................................320mW (Depend on package)
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
Symbol VCC VIH VIL TA Power voltage Input high level Input low level Operating temperature Description Min 2.0 0.7 VCC -0.3 -40 Type Max 5.5 VCC+0.3 0.3 VCC 85 C V Unit
PT0222(02/06) 13
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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DC Electrical Characteristics
(Unless otherwise specified, VCC = 2.0 ~ 5.5 V, TA = -40 C to +85 C.)
Sym.
VCC VBAT1
Item
Supply voltage Supply voltage Condition for VCC switch to VBAT Condition for VBAT switch to VCC Current consumption Standby current Current consumption Low-level input voltage High-level input voltage Low-level output voltage Input leakage current Output current when OFF
Pin
VCC VBATT -
Condition
Min
2.0 2.5 -
Typ
3 VCC < VBAT 0.1v VCC > VBAT
Max
5.5 3.5 -
Unit
V V V
VSO
2
VCC VCC VBAT
Switch freq. = 100kHz SDA, SCL = VCC - 0.3V OSC on, VCC = 0V, VBAT = 3V, TA=25C -0.3 0.7VCC
ICC IST IBAT VIL VIH VOL IIL IOZ
300 150 650 800 0.3VCC VCC +0.5 0.4 1 1
A A nA V V A A
SDA SCL SDA
IOL = 3mA 0Note: 1. After switchover (VSO), VBAT(min) can be 2.0V for crystal with RS=40k. 2. Switch-over and deselect point.
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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AC Electrical Characteristics
Sym VHM VHL Description Rising and falling threshold voltage high Rising and falling threshold voltage low Value 0.8 VCC 0.2 VCC Unit V V
Signal VHM VLM
tf
tr
Over the operating range Symbol fSCL tSU;STA tHD;STA tSU;DAT tHD;DAT1 tHD;DAT2 tSU;STO tBUF tLOW tHIGH tr tf tSP* CB SCL clock frequency START condition set-up time START condition hold time Data set-up time (RTC read/write) Data hold time (RTC write) Data hold time (RTC read) STOP condition setup time Bus idle time between a START and STOP condition When SCL = "L" When SCL = "H" Rise time for SCL and SDA Fall time for SCL and SDA Allowable spike time on bus Capacitance load for each bus line Item Min. 0.6 0.6 200 35 0 0.6 1.3 1.3 0.6 0.3 0.3 50 400 Typ. Max. 400 Unit kHz s s ns ns s s s s s s s ns pF
* Note: Only reference for design.
S SCL tLOW fSCL tHIGH
Sr tHD;STA tSP
P
tSU;STA
tBUF
SDA tHD;STA tSU;DAT tHD;DAT tSU;STA tSU;STO tHD;STA
S Sr
Start condition Restart condition
P
Stop condition
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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Mechanical Information
W/WE 8-Pin SOIC 8 .0099 0.25 o .0196 0.50 x 45
.149 .157
3.78 3.99 0-8o
.0075 .0098 0.40 1.27 .016 .050
0.19 0.25
1 .189 .196 4.80 5.00
.2284 .2440 5.80 6.20 .053 .068 1.35 1.75 SEATING PLANE X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS
.016 .026 0.406 0.660 REF .050 BSC 1.27
.0040 .0098 .013 0.330 .020 0.508
0.10 0.25
Note: 1) Controlling dimensions in millimeters. 2) Ref: JEDEC MS-012 AA
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Data Sheet PT7C4300 Real-time Clock Module (I2C Bus)
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Notes
Pericom Technology Inc.
Email: support@pti.com.cnWeb Site: www.pti.com.cn, www.pti-ic.com China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 3545 North First Street, San Jose, California 95134, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Asia Pacific:
U.S.A.:
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation.
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